发明名称 GRAPHIC DISPLAY SYSTEM FOR PROCESS CONTROL USING A PLURALITY OF DISPLAYS CONNECTED TO A COMMON PROCESSOR AND USING AN FIFO BUFFER
摘要 A graphic display system comprising a plurality of graphic display units which are connected to a host processor through a common bus and providing useful quick response characteristics as a man-machine interface for process control, wherein a common memory of two ports, one of which is connected to the common bus and the other is connected to an internal bus, is provided in each graphic display unit and a part of the common memory is used for transmission of high level command/data with the host processor and comprises a FIFO (i.e. first in first out) buffer.
申请公布号 US5065343(A) 申请公布日期 1991.11.12
申请号 US19890311007 申请日期 1989.02.14
申请人 YOKOGAWA ELECTRIC CORPORATION 发明人 INOUE, KENICHI
分类号 G06F3/14;G06F3/153;G06F9/445;G09G5/02;G09G5/06;G09G5/14;G09G5/34;G09G5/36;G09G5/39;G09G5/397;G09G5/40 主分类号 G06F3/14
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