发明名称 DEVICE AND METHOD FOR GENERATING TEST PATTERN
摘要 PURPOSE:To improve working efficiency in the generation of a test pattern by performing the setting of an assumptive fault, the decision of a signal route to propagate a fault, that of the value of an element, recovery when the propagation of the fault is disabled in the middle way in interactive fashion. CONSTITUTION:A processing part 3 stores command information in a temporary storage part 4, and also, performs fault propagation processing in the generation of the test pattern in accordance with a command. The temporary storage part 4 is the one to store history information in a process to find the test pattern for one fault, and it stores, for example, a propagation route, the logical values of input and output signals of the element, and fault information such as a fault value, etc. A storage part 5 stores logical connection information consisting of at least two hierarchies, logic circuit plotting information, and test pattern information, etc., and a display part 6 displays a logic circuit diagram and a fault propagation route, the logical value and the fault value, and selective support information for a branch signal, etc., based on the command from the processing part 3. Thereby, the test pattern can be obtained with high efficiency.
申请公布号 JPH03252730(A) 申请公布日期 1991.11.12
申请号 JP19900049299 申请日期 1990.03.02
申请人 HITACHI LTD 发明人 KOJIMA SEIYA;HATAKEYAMA KAZUMI;KIYOSHIGE KENICHI
分类号 G06F11/22;G06F17/50 主分类号 G06F11/22
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