| 摘要 |
PURPOSE:To reduce the dispersion in a delay time and a pulse width by selecting a pulse generating period of a shift signal sufficiently shorter than a prescribed time difference to be delayed. CONSTITUTION:A shift register 62 fetches a signal AZ synchronously with a clock signal CLK and stores the content into a register and shifts the storage content of the register one by one and outputs the storage content from a preset n-th register. Since a pulse production period PT2 of the clock signal CLK is a sufficiently shorter period than a constant time difference tauD to be delayed, the dispersion in a delay time and a pulse width is small. Thus, dispersion in the pulse width of PWM signals E3, F3 obtained finally and of the pulse generating timing goes to less and transistors(TRs) 1, 2 being a couple of controlled elements are subject to switching control with a high accuracy. |
