| 摘要 |
<p>PURPOSE:To optimize a timing between write and read clocks in a buffer memory by providing a voltage control oscillator, a speed conversion multiplex circuit, a clock frequency divider and a timing correction means. CONSTITUTION:A voltage is applied to an external voltage control terminal 5 from outside, the frequency of the voltage control oscillator (VCO) 4 is fixed, and a secondary clock from VCO 4 is frequency-divided in the clock frequency divider 6 so as to generate a primary clock. A clock cancel circuit 9 cancels the secondary clock inputted to the clock frequency divider 6 for time decided in a time constant circuit 8 with the asynchronous detection output ASYNC of the primary clock and the secondary clock, which are provided in the speed conversion multiplex circuit 1, as triggers. While the secondary clock is cancelled, the clock frequency divider 6 stops and digital data and the primary clock, which are inputted to the speed conversion multiplex circuit 1, are stopped. On the other hand, the secondary clock from VCO 4 to the speed conversion multiplex circuit 1 is always inputted. Thus, the shift of the write/ read timing of the buffer memory can be corrected and it is made appropriate.</p> |
