| 摘要 |
PURPOSE:To dispense with unrequired thinning processing and to perform conversion at high speed by shifting data with plural shift registers and a FIFO, and providing a means which detects no change in the data in one time of circulation. CONSTITUTION:The shift registers 1-4 of plural stages sequentially shift added data of N bits, and a memory 5 on which the data to be stored in the registers 1-4 are added as addresses outputs the data stored in advance. The FIFO 7 stores the data outputted from the memory 5, and also, adds the data stored previously on the initial stage of the shift registers 1-4 of plural stages. A detecting means 6 compares a part of the data to be added on the address of the memory 5 with the output of the memory 5, and detects the fact that no change occurs in shifted data in one time of circulation in the plural shift registers 1-4 and the FIFO 7. In such a way, it is possible to obtain a data conversion circuit from which the unrequired thinning processing is eliminated and in which fast data conversion can be performed. |
