Devices having shallow junctions

摘要

In CMOS based integrated circuits, stricter design rules require source and drain junctions shallower than 2500 ANGSTROM . By using a specific device configuration, a shallow junction is obtainable while resistance to latch-up is improved and other electrical properties, e.g., low leakage current, are maintained. To achieve this result the p-channel device should have an activation energy of the junction reverse leakage current region less than 1.12 eV, with a junction dopant region shallower than 1200 ANGSTROM and a monotonically decreasing junction dopant profile.