| 摘要 |
<p>A voltage-controlled delay (418) is connected in series with a phase-locked loop (430). The voltage-controlled delay is controlled by the control voltage developed by the phase-locked loop amplifier and filter (410). With this arrangement, the amplifier and filter can be designed to have a transfer function that does not include an explicit zero. Consequently, the jitter transfer function of the overall structure can be designed to remain equal to or less than unity over all frequencies and jitter peaking is eliminated.</p> |
