发明名称 SEMICONDUCTOR MEMORY CIRCUIT
摘要 <p>PURPOSE:To obtain a useful element layout and to increase the size of a chip, by using one optional input signal to an address decoder ciruit for the earth line selection of a memory cell. CONSTITUTION:When a clock signal phi is at a level H and the most significant digit input sgnal Axn to an X address decoder circuit is at a level L, a phi1 goes down to the level L, and n channel MOSFETs 30, 34... turn off to separate each drain electrode terminal from the earth, therehy making a MOSFET20 ineffective. Further, a phi2 goes up to the level H, and n channel MOSFFETs 32, 36... turn on to ground each drain electrode terminal, thereby making the MOS20 effective. Then when one of output terminals Xo-Xn for an X address of an X decoder circuit is at the level H, an FET turns on unless it is connected to the terminal, and a data line is grounded to generate an L-level output. when the FET is not connected, the data line holds itself at the level H.</p>
申请公布号 JPS5766595(A) 申请公布日期 1982.04.22
申请号 JP19810119209 申请日期 1981.07.31
申请人 OKI DENKI KOGYO KK 发明人 YOSHIDA TERUHIRO
分类号 G11C17/00;G11C17/12;H01L21/8246;H01L27/112 主分类号 G11C17/00
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