| 摘要 |
Reduced integration time within a lead-lag compensation circuit within a disk drive head positioner servo loop is reduced in the presence of a feed back position error signal which includes a bias force component. The compensation circuit including an integrating capacitor and a high value resistor through which the integrating capacitor is charged by the position error signal. Charging time of the integrating capacitor is reduced during track settling by a parallel resistance switchably connectable across the high value resistor for lowering the resistance thereof. A switch, such as a field effect transistor in series with the parallel resistance, connects the parallel resistance across the high value resistor in response to a switching signal. A control circuit, such as a system microprocessor, is responsive to the head positioner servo loop and generates the switching signal to cause the switch to connect the parallel resistance means across the high value resistor during a settle interval immediately following completion of track seeking when the servo loop is functioning in a track following mode and before track seeking is complete.
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