发明名称
摘要 PURPOSE:To enable to minimize the width of power supply line by a method wherein the number of cells changing at the same hour when the cells are connected to the same power supply lines is limited to a specified value. CONSTITUTION:Assuming signals IN1, IN2, IN3 and IN4 to be respectively inputted into a signal line 42 with their phases being shifted within a block 4 arranged with 4 each of cells 41 for timing distribution, the signals from OUT1, OUT2, OUT3 and OUT4 are outputted respectively into output signal lines 43. At this time, the current flows in power supply lines 441-444 as shown in iB1-iB4 i.e. at a specified hour, the power supply line 44 is supplied with the current flowing in only one each of cell 41 as shown in iB. Within an integrated circuit 5 arranged with 4 each of blocks 4, the power supply lines 521-524 are supplied with the current flowing in one each of cell 41, while at a specified time, the power supply 52 is supplied with the current flowing in only two each of cells 41.
申请公布号 JPH0367341(B2) 申请公布日期 1991.10.22
申请号 JP19850053848 申请日期 1985.03.18
申请人 HITACHI LTD 发明人 OKABE TOSHIHIRO;YAMAGIWA AKIRA
分类号 H01L21/822;G06F17/50;H01L21/82;H01L27/04 主分类号 H01L21/822
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