| 摘要 |
<p>PURPOSE:To reduce the lock time, to expand the tracing range and to attain stable phase clock output by using a phase comparator and an up-down counter so as to detect a phase difference between input and output signals and selecting an optimum value of a frequency division ratio in response to the phase difference. CONSTITUTION:A phase comparator 1 receives an input signal S1 from a terminal T1 and an output signal S0 from a terminal T0, compares the phases of the both and an UP signal U or a DOWN signal D whose phase difference corresponds to a time difference of the input and output signals is outputted. An up-down counter 2 receives the signals U, D and up or down-counts each pulse width by using a clock pulse CP. A filter 3 receives a digital count of the signal A from the counter 2, averages the phase difference of the succeeding digital count to output an averaging digital phase difference B. A decoder 4 decodes the phase difference mean value B being an output of the filter 3 and outputs a frequency division ratio designation signal C designating the frequency division ratio of the frequency divider 5. The frequency divider 5 divides a reference signal SR by using the signal C and generates a pulse train of the signal S0.</p> |
