ON CHIP SEMICONDUCTOR MEMORY ARBITRARY PATTERN, PARALLEL TEST APPARATUS AND METHOD

摘要

An apparatus for parallel testing of a semiconductor memory with arbitrary data patterns and capable of being integrated on the memory chip. The semiconductor memory test device in a preferred embodiment is compatible with hierarchical data bus lines including an input/output line pair (I/O, I/O), a plurality of sub-input/output line pairs (SIO1+L, SIO1; SIO2, SIO2) and a plurality of bit line pairs (BL1, BL1; BL6, BL6). A plurality of comparators (50) and a plurality of registers (60) are provided corresponding to a plurality of sub-input/output line pairs (SIO1, SIO2; SIO2, SIO2). The plurality of registers (50) which also functions as intermediated output amplifiers can hold random data applied through the input/output line pair (I/O, I/O). The plurality of comparators (60) is provided to determine whether or not data read out onto a plurality of sub-input/output line pairs (SIO1, SIO1; SIO2, SIO2) from a row of memory cells (MC1, MC2) corresponding to a single word line (WL) match respective data held in the plurality of registers (60).