| 摘要 |
PURPOSE:To eliminate glitch by forming the circuit with a D flip-flop (D-FF), a capacitor and a resistor R only and preventing a short width pulse from being outputted by a time constant. CONSTITUTION:When a clock enters a point C, a signal at a terminal D is outputted to a terminal of a D-FF 8 by a leading edge of the point C and a terminal output Q goes to H, and since the point C is charged to a high level at a resistor R9 of the D-FF 8, the level at a point D goes to H. The level at the point D is discharged by a time constant comprising a capacitor C10 and the resistor R9 and the D-FF 8 is reset. When the pulse with a low level and a short interval is inputted to the input, the reset at the point D is released. Moreover, when a short interval pulse is inputted at a high level, since the timing when the output Q goes to L depends on the time constant comprising the capacitor C10 and the resistor R9, the output Q goes to an L level after a prescribed time. |
