| 摘要 |
The synchronous pattern detecting circuit detects the receiving synchronous pattern in the stream that are alternately inserted and transmitted by the first receiving synchronous pattern which includes a frame array signal and the second receiving synchronous pattern which does not include a frame array signal to avoid a copy of the frame array signal on receiving a digital line. The circuit of present invention comprises a synchronous pattern extracting circuit (10), a inverter (5), three flip-flops (20,30,40), a status clock extracting part (50), three synchronous transition status data extracting parts (60,70,80), a synchronous status detecting part (90), and a remote alarm circuit (100).
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