Integrated data link controller with autonomous logical elements.

摘要

A single chip integrated data link control (IDLC) device provides full duplex data throughput and versatile protocol adaptation between variably configured time channels on a high speed TDM digital link (e.g. T-1 or T-3 line) and a host data processing system. The device handles multiple channels of mixed voice and data traffic concurrently, and thereby is suited for use in primary rate ISDN (Integrated Services Digital Network) applications. Synchronous and asynchronous sections in the device respectively interface with the network and host system. Special purpose autonomous logic elements in the synchronous section form plural stage receive and transmit processing pipelines between the network and host interfaces. Such pipelines perform OSI Layer 2 processing tasks on data in HDLC channels. Each autonomous element comprises one or more state machine circuits having functional autonomy and reduced time dependence relative to other elements. A "resource manager" element (RSM) and time swap (TS) RAM memory operate to dynamically swap states of pipeline elements in synchronism with channel time slots at the network interface, whereby the pipeline stages operate as data buffering stages which perform multiple tasks during any slot. The device contains integrated memory queues in which communication data and channel event status information are stacked for asynchronous transfer. Capacities and modes of operation of these queues are selected to minimize effects on chip size, throughput and cost, while minimizing critical time dependencies between the device and host system. Device elements provide first and second non-interfering information transfer paths between the device and host system; one for exchanges of control/status information between the device and host, and the other for direct memory access transfers of communication data between the device and an external memory associated with the host.