| 摘要 |
A power integrated circuit having an improved trade-off between on-state resistance and break down voltage. The circuit contains multiple devices, disposed over a drain electrode, including a vertical double-diffused MOS(VDMOS) translator having a buries layer of low resistivity interposed between an n30-type substrate and an n--epitaxial layer in the current path between the drain electrode and the source. The on-state resistance of the integrated circuit is lowered by the provision of the buried layer, while the breakdown voltage of the integrated circuit is heightened by making the resistance of the n--epitaxial layer high. |
