| 摘要 |
PURPOSE:To efficiently perform the functional test of a dynamic (D) RAM having large column address space by providing capacitors for reference bit and check bit and a collation circuit, etc., at every data line. CONSTITUTION:The check bit of the check capacitor Cc of the collation circuit DCL in a memory array ARYL at every data line DL1, inverse of DL1, DL2, inverse of DL2... is reset, and test bit data is written on the reference capacitor Cr of a sense amplifier SA. The data is transferred to the capacitor Cs of a memory to be tested in the sense amplifier SA in unit of word lines WL 1-WLm, and is read out in unit of word lines WL1-WLm, and is compared with reference bit data held with the capacitor Cr at a corresponding circuit DCL, and is written on the check bit capacitor Cc of the circuit DCL corresponding to a collated result. The same operation is performed on a memory array ARYR, thereby, it is possible to efficiently perform the functional test of the DRAM having large column address space at every data line. |
