发明名称 TROUBLE POSITION POINT-OUT METHOD
摘要 PURPOSE:To improve the point-out accuracy of a trouble position by extracting previously the data on the circuit state via a trouble analyzing subject computer, performing the logical simulation based on the extracted data on the circuit state, ad comparing the obtained circuit state of a normal mode with the circuit state of a trouble mode. CONSTITUTION:A trouble detecting computer system contains the trouble analyzing subject computers 1 - 3 connected to a single trouble analyzing computer 4. The circuit states of computers 1 - 3 are extracted and stored for each prescribed time, and the due processing is started at occurrence of troubles of computers 1 - 3. Then a logical simulator 15 performs the logical simulation of the circuit states of the computers 1 - 3 based on the stored circuit states set before occurrence of the trouble. A comparison processing part 14 compares successively the simulated circuit states with those of the stored ones. Based on these comparison results, the trouble positions of the computers 1 - 3 are pointed out.
申请公布号 JPH03217947(A) 申请公布日期 1991.09.25
申请号 JP19900013205 申请日期 1990.01.23
申请人 HITACHI LTD 发明人 KUROSAKI MASATO;OKAZAKI YOSHINOBU;MORI TERUO;YOSHIZAWA KAZUO
分类号 G06F11/22 主分类号 G06F11/22
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