| 摘要 |
<p>PURPOSE:To output a clock pulse at a delay within a half clock pulse by applying the clock pulse of an opposite phase to each clock input of two-flip-flops, and validating only a flip-flop set when a control signal for pulse generation is started to use as a data input is supplied. CONSTITUTION:When a main clock pulse MCK of a positive phase is fed to a flip-flop 51 in a couple of D flip-flops 51, 52, a main clock pulse of a negative phase passing through an inverter 53 is fed to the flip-flop 52. Inhibit means 55, 60 are provided respectively to the flip-flops 51, 52 and the inhibit means 55, 60 are operated to validate the flip-flop 51 or 52 only set early to logical '1' to a control signal TRG commanding the start of pulse generation. Since the main block pulses MCK in opposite phase are delayed only by a half clock mutually, a synchronization clock signal CLK is obtained by the delay of a half clock at maximum by a trigger signal TRG is obtained.</p> |
