| 摘要 |
<p>A single-chip microcomputer (19) has a clock-signal generating circuit (14) which includes a main system-clock oscillation circuit (5) for generating a main clock-signal (102), a sub system-clock oscillation circuit (4) for generating a sub clock-signal (101), a selector flag setter (3) for setting a selector flag, an oscillation control flag setter (2) for setting an oscillation control flag, and a synchronization control circuit (6) for effecting synchronization between the main clock-signal (102) and the sub clock-signal (101). The clock-signal generating circuit (14) of the invention has a logic circuit which takes an logical AND operation of outputs of the oscillation control flag setter (2), the selector flag setter (3) and the synchronization control circuit (6) and which outputs an oscillation control signal (120) for stopping oscillating operation of the main system-clock oscillation circuit (5). The main system-clock oscillation circuit automatically stops upon completion of the clock-signal switching operation, so that a CPU does not require a stand-by period for the switching of clock-signals and this results in the enhancement of processing capability of the CPU and results in the reduction of the power consumption. <IMAGE></p> |
