| 摘要 |
<p>A CMOS array multiplier cell comprising two CMOS equivalence circuits for sum generation, two pass transistors and an inverter for carry generation, and a multiplier selector built of a matrix of identical selection elements, a single FET switch and an inverter. Each of the selection elements consists of an N-channel FET, a P-channel FET and an inverter. Each equivalence circuit utilizes six transistors: four FET's and an inverter. Total cell device count is 31 to 39 transistors, depending on implementation alternatives. <IMAGE></p> |
