发明名称 SEMICONDUCTOR MEMORY TEST DEVICE
摘要 PURPOSE:To simultaneously store test results of first and second test heads for plural memory elements in independent fail memories by operating OR among logic comparison results of one memory for plural pins. CONSTITUTION:Four memory elements 121 to 124 to be tested are mounted on a first test head 11, and memory elements 141 to 144 to be tested are mounted on a second test head 13. A test pattern is given from a pattern generator 15 to memory elements 121 to 124 and 141 to 144, and its data is written in addresses, and written data is read out and has the logic compared with expected values by logic comparing circuits 161 to 164 and 171 to 174 with respect to each pin. These logic comparison results are stored in fail memories 251 and 252 through multiplexers 18 to 23. Thus, test results of first and second test heads for plural memory elements are simultaneously stored in independent fail memories.
申请公布号 JPH03209183(A) 申请公布日期 1991.09.12
申请号 JP19900004095 申请日期 1990.01.10
申请人 ADVANTEST CORP 发明人 KANAI JUNICHI
分类号 G01R31/28;G01R31/3193;G06F11/22;G11C29/00;G11C29/56 主分类号 G01R31/28
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