Multiplier circuit for digitally coded numbers - has part stages coupled to shift register generating outputs

摘要

A digital multiplier system operates on numbers in 52 code and has a main matrix multiplier circuit (1) that combines with adder circuits (2,3). Carry propagation is handled by a number of coupled adder stages (4) and all units provide outputs to a shift register (5b). The shift register provides for parallel inputs and effects a shift to the right data to generate a multibit output. A controller unit provides operation of the stages and includes a programmable counter. ADVANTAGE - Efficient part product addition.