| 摘要 |
PURPOSE:To prevent the occurrence of malfunction of a communication control section and to improve the quality and cost by providing flip-flops FFA, FFB transferring an input to an output at a rising edge from 0 to 1 of timing signals CK1, CK2 respectively and a signal passing circuit. CONSTITUTION:While a selective signal SEL at first is logic '1', a timing signal CK1 is selected and outputted as a CLKa. When the SEL changes to 0, an input signal S11a of a flip-flop FFA goes immediately '1' and an output S12a of the FFA transits from '0' to '1' at the rising edge from '0' to '1' of the succeeding CK1. Since a NOR gate NOA receives the signal S12a and the clock CK1, its output S13a goes to '0'. In this case, the FFA has a time delay, then the pulse width of the signal S13a just before the switching is identical to the pulse width of '0' of the CK1. Thus, the timing signal is switched and no short width pulse is generated even in the moment of switching. |
