Integrated circuit.

摘要

A high density segmented programmable array logic device utilizes a programmable switch interconnection matrix (401) to couple an array of symmetric programmable logic blocks (402A-1,402A-2).Each programmable logic block includes programmable logic macrocells (4122), programmable input/output macrocells (4132), a logic allocator (4112) and a programmable product term array (4102). Further, the switch matrix (401A) provides centralized global routing with a fixed path independent delay. The programmable switch interconnection matrix (401A) decouples the logic macrocells (4122) from the product term array (4102). The logic allocator (4112) decouples the product term array (4102) from the logic macrocells (4122) and the I/O macrocells (4132) decouple the logic macrocells (4122) from the package I/O pins (403A-1,403A-2). Thus, the architecture if this invention is easily scalable to higher density devices without compromising speed. The logic allocator (4112) steers product terms from the product term array (4102) to selected logic macrocells (4122) so that no product terms are permanently allocated to a specific logic macrocell. <IMAGE>