| 摘要 |
A semiconductor memory device, with redundancy device, prevents access time of a row address from being delayed in a normal operation mode. By using a mode detect signal generated by detecting whether or not the memory device will be repaired, the row address is directly accessed without passing through a delay circuit in the normal operation mode, while the access of the row address is delayed in the redundant operation mode. To this end, the device comprises a detecting circuit for generating the mode detect signal MD in dependence upon turning on/off of a fuse 116, a first transfer path 201 transferring a buffered row address without delay, a second transfer path 202 delaying the buffered row address through a delay circuit 130, and a path select circuit 120 selecting either the first transfer path 201 or the second transfer path 202 in dependence upon the mode detect signal MD, to transfer a signal of a selected path to a boost clock generator. <IMAGE> |
