发明名称 CLOCK PATH SWITCHING SYSTEM
摘要 <p>PURPOSE:To secure a communication between nodes by sending out the free- running output of a clock oscillator which oscillates by itself in a normal direction by a subordinate node which is sited between two fault points and receives a clock sent back in the opposite direction from the normal direction. CONSTITUTION:A node B generates a clock signal of the same frequency with a received clock CK1 from a main node A through a clockwise transmission line 1R in subordinate synchronism with the clock CK1 and sends the clock signal out to a next node C through a clockwise transmission line 1S. If a clockwise transmission line to a next node D, however, is faulty and disconnected, the node C sends the received clock CK1 back to a counterclockwise transmission line 2S in the opposite direction from the normal direction and disconnects the faulty point. When the counterclockwise transmission line 2S is faulty and disconnected, the node D at a reception terminal oscillates a signal of the same frequency as the oscillation frequency before the node C disconnects the clockwise transmission line 2S by itself and sends its free-running output to the clockwise transmission line 1S while supplying the clock to its multiplexing device MX to serve as a main node temporarily. Consequently, the communication between the nodes C and D is secured.</p>
申请公布号 JPH03207138(A) 申请公布日期 1991.09.10
申请号 JP19900001925 申请日期 1990.01.09
申请人 FUJITSU LTD 发明人 TANIGUCHI TAKAYUKI
分类号 H04L5/22;H04J3/06;H04L7/00 主分类号 H04L5/22
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