Semiconductor memory circuit device having gate array memory cells.

摘要

A semiconductor memory circuit device having gate array memory cells (2) includes amplifying means constituted by a bipolar transistor (Tr1, Tr3) connected to the output stage of each of memory cells arranged in a matrix form on a semiconductor substrate (1) and formed in a gate array memory cell configuration by use of the Master slice approach. The amplifying means (Tr1, Tr3, R1, R2) amplifies the potential level of readout data of the memory cell (2) and output the same to an output line (18, 19), thus enhancing the driving ability of the output line (18, 19) and reducing the whole readout time for reading out data from the memory circuit. <IMAGE> <IMAGE>