| 摘要 |
The circuit latches the data address and control signal of the system memory, and the I/O data address and control signal to ease the error checking and the state discrimination. The method includes steps: (A) initializing each units by a control signal of a CPU; (B) testing the state of data inputting and outputting in serial; (C) discriminating the correctness of the state of data; (D) testing the operation state of the CPU by loading a first test program when the state of data is correct and loading a second test program otherwide; (E) displaying the operation errors of the CPU when the operation state is incorrect and testing the CPU again when the error value does not reach a threshold; (F) testing the state of ROM when the state of the CPU is correct, and displaying and storing the error otherwise and testing the control state of ROM; and (G) testing the external memory data and address bus, and external I/O data and address bus when the RAM is normal, and storing and displaying the error otherwise.
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