| 摘要 |
PURPOSE:To reduce the plane area of a memory cell by a method wherein the surface on the inside of a groove formed in a semiconductor substrate is used as an isolation insulating film between memory cells and two capacity parts are formed on the inside of the groove. CONSTITUTION:A desired pattern is formed on a P-type silicon semiconductor substrate 1; after that, a perpendicular groove is formed; and an insulating film 2 to be used as an insulating isolation layer is formed on the inside of the groove and in one part of the substrate 1. A first conductor layer 3 to be used as an electrode of a capacity part is formed on the insulating film 2; a first dielectric layer 4 is formed on the first conductor layer 3; a second conductor layer 5 to be used as a capacity electrode of a definite potential is formed on the first dielectric layer 4; a second dielectric layer 6 is formed on the second conductor layer 5; and a third conductor layer 7 to be used as an electrode of a capacity part is formed on the second dielectric layer 6. Thereby, it is possible to reduce the area of a memory cell. |
