发明名称 FREQUENCY DIVISION CIRCUIT
摘要 <p>PURPOSE:To attain optional irregular frequency division by writing a frequency division data to a ROM in advance, reading it and shifting the data one by one bit each. CONSTITUTION:A reference clock 16 outputted from a reference clock output circuit 11 passes through a counter 15 and one clock in X clocks is inputted to a ROM pointer 12. The ROM pointer 12 is incremented for each input of the clock, the value is used as an address for the ROM 13, X bits are read by each increment of the address of the ROM 13 and inputted to a shift register 14. The shift register 14 shifts a data in the X bits for each clock of the reference clock 16 by one each and outputs the result. Thus, optional irregular frequency division is implemented.</p>
申请公布号 JPH03190427(A) 申请公布日期 1991.08.20
申请号 JP19890330583 申请日期 1989.12.20
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 SAKAKIBARA MIKIO
分类号 H03K3/78;G06F1/06;H03K21/00 主分类号 H03K3/78
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