| 摘要 |
PURPOSE:To improve the application efficiency of hardware by using the mode signal which prescribes the memory unit number to correct the difference between address information on the final element of the 1st data and that on the head element of the 2nd data. CONSTITUTION:An adder circuit 1 calculates a bank address 2 of the data final element and supplies it to a register 2. A subtractor circuit 3 uses a mode signal which prescribes the memory unit number to calculate the difference between the bank addresses of the final and head elements of the data gives from the register 2 and supplies the obtained difference to a gate circuit 4. A shift circuit 5 shifts the difference between bank addresses masked by the circuit 4 and supplies it to a subtractor circuit 6. The circuit 6 subtracts the difference between shifted bank addresses from the information on the memory bank cycle time and supplies the result of this subtraction to a gate circuit 7. Then the waiting cycle number is led out of the circuit 7. |
