| 摘要 |
<p>A digital-to-analog converting unit fabricated on a single semiconductor chip comprises a string (91) of resistive elements (R, R/2) coupled between a source of power voltage level (Vdd) and a source of ground voltage level (GND) and an array (92) of switching elements (S2) respectively associated with intermediate nodes each provided between every adjacent two resistive elements, and each of the switching elements is implemented by a parallel combination of an n-channel type component field effect transistor and a p-channel type component field effect transistor even if one of the component field effect transistors of the switching elements near the voltage sources remains off at all times, because the parallel combinations enhances uniformity of pattern on the semiconductor chip, thereby preventing the string of the resistive elements from irregularity of sheet resistance. <IMAGE></p> |
