| 摘要 |
<p>A microcomputer system memory architecture and method allows the system memory (102,202) to provide data access at high speeds in a burst mode. The architecture and method utilizes a system memory controller (308) capable of performing the addressing of the system memory (102,202). The microprocessor (106,206) and the system memory (102,202) communicate via a high speed host bus (104). The system memory (102,202) is comprised of multiple 64-bit system memory buses (1-N; 211,212) to permit high speed data transfer to the microprocessor (106,206) in a burst mode without the need for an external cache. <IMAGE></p> |
