| 摘要 |
In an encoder replica of a decoder for an input code sequence which corresponds to a code symbol sequence comprising an information symbol sequence and a redundancy bit sequence, a one-bit memory (46) successively memorizes consecutive bits of the input code sequence as memorized bits. An output circuit (62) delivers replica output bits in bit series to a sequential decode controller (43) in response to the memorized bits. In response to the memorized bits and a control signal produced by the controller in response to the input code sequence and the replica output bits, the encoder replica decodes the input code sequence into a reproduction of the information symbol sequence. Preferably, the output circuit is controlled by a position counter (64) giving separate indication of bits corresponding in the input code sequence to the information symbol sequence and of bits corresponding in the input code sequence to the redundancy bit sequence. More preferably, a synchronism shift counter corrects the separate indication in consideration of a shift in synchronism of the separate indication relative to the input code sequence. |
