| 摘要 |
PURPOSE:To decrease the number of component elements and to reduce the scale of a wallence tree circuit by handling the input values of a full adder and a half adder in terms of a negative logic. CONSTITUTION:A full adder 700 consists of the AND circuits 710 - 730, a NOR circuit 740, and the exclusive OR circuits 750 and 760 and receives the supply of the inverted inputs A - C. The circuit 740 outputs the carry output C which is supplied to the next stage, and the circuit 760 outputs the addition output S. The inverted inputs A and B are supplied to a NOR circuit 810 and an AND circuit 820 via a half adder 800. The output of the circuit 810 is used as the output C and at the same time this output C and the AND output are supplied to a NOR circuit 830 to undergo the NOR processing and to be used as the output S. As a result, the number of component elements can be decreased for both adders 700 and 800. Then the scale of a wallence tree circuit is reduced. |
