| 摘要 |
PURPOSE:To reduce the number of elements used, simplify wiring between elements, reduce power consumption and increase operation speed by constituting a carry look ahead circuit in multi-bit binary number parallel addition of a complementary circuit. CONSTITUTION:A carry look ahead circuit in parallel addition of binary number 3 bits is constituted symmetrically of a logical circuit 150, a complementary invertor and PMOS transistors 114-127. In this look ahead circuit, when sending carry signal output COUT3 by carry input CIN, configuration of the circuit 150 is simple, almost all nodal point capacity is very small, and load driving capacity of the circuit 151 is large. Accordingly, it becomes possible to make operation speed of the carry look ahead circuit high. As circuit configuration is simple, it can have a high operation speed and expansibility, and can be constituted of small number of elements. Further, as wiring between elements is simple, power consumption can be reduced. |
