| 摘要 |
PURPOSE:To achieve secure A/D conversion in any case by performing either one of the 1st A/D conversion and 2nd A/D conversion when a request for the 2nd A/D conversion is made during the 1st A/D conversion while the operation state of an A/D converter is monitored by an FF circuit. CONSTITUTION:If an interruption request signal is generated synchronizing with the prescribed period of an aperiodic timer while an A/D converter 6 performs A/D conversion, a microcomputer 1 judges that the converter 6 is in operation since an A/D-conversion start signal ADS raises on a signal line 10, and then stores a channel signal which corresponds to the interruption signal in a memory RAM. Once the 1st A/D conversion ends, the converter 6 supplies a request signal EIS for conversion-end interruption to the computer 1 through a signal line 12, a control circuit 8 and a signal line 14 to execute an interruption program. At this time, a conversion end signal CES is supplied to the reset terminal of an FF21 through the signal line 12, so the Q output of the FF21 falls down to a 0. |
