| 摘要 |
PURPOSE:To operate information processors simultaneously and accurately by delaying the start or stop signal of one system by the extent of delay selected among the extents of delay, and thus canceling delay with other systems. CONSTITUTION:When the delay time of a signal transmitted from a system A to B is 2gamma, set signals 0 and 1 by a setting circuit 11 are latched by latch circuits 12 and 13 for the simultaneous start of both the systems. Once a counter circuit 20 counts up by 3gamma, the start of the system A is commanded. On the other hand, a start indication signal to be transferred to the system B is delayed by 2gamma through a signal line L1, and supplied as a signal S2 to the input of a latch circuit 21. The circuit 21 is commanded by a next clock signal pulse to start the system B. The system B is started 3gamma after the setting of the system A by a start indication signal, i.e. simultaneously with the system A. |
