发明名称 |
MESSAGE FIFO BUFFER CONTROLLER |
摘要 |
MESSAGE FIFO BUFFER CONTROLLER A FIFO (first in first out) control circuit for providing address information to a FIFO memory. Two up counters are used; one to provide the write address and one to provide the read address. A multiplexer selects which addresses (read or write) are used. Two storage registers are used to temporarily "hold" the output from the counters. This enables the counters to be re-loaded with their original "count" to enable either a re-reading or a re-writing of a message stored in the FIFO memory. Logic circuitry is used to provide two status output signals, namely full (or not) and empty (or not).
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申请公布号 |
CA1286421(C) |
申请公布日期 |
1991.07.16 |
申请号 |
CA19870549274 |
申请日期 |
1987.10.14 |
申请人 |
BELL-NORTHERN RESEARCH LTD.;NORTHERN TELECOM LIMITED |
发明人 |
LEFEBVRE, MARTIN C.;CIANCIBELLO, CARMINE A.;GEADAH, YOUSSEF A. |
分类号 |
G06F5/10;G06F5/14;G11C7/00;(IPC1-7):G11C5/00 |
主分类号 |
G06F5/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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