发明名称 POWER-ON RESET CIRCUIT
摘要 PURPOSE:To achieve a reset output not affected with the rising characteristics of a power supply voltage, by connecting a capacitor to a connecting point of switches in series connection driven complementarily and a switch output, and taking the voltage of a capacitor connected to the output as reset output through detection. CONSTITUTION:A power supply is applied and given to a terminal 1. When the voltage reaches a specified voltage, a clock pulse is generated and this clock pulse turns on switches 6, 7 complementarily. Thus, the terminal voltage of a capacitor 9 is stepwise increased every time the clock pulse is applied. A reset output can be obtained at an output terminal 5 until this voltage exceeds the threshold level of a gate circuit 4.
申请公布号 JPS57115030(A) 申请公布日期 1982.07.17
申请号 JP19810001166 申请日期 1981.01.09
申请人 NIPPON DENKI KK 发明人 KIKUCHI KOUICHI;SHIODA FUMIO
分类号 H03K17/22;(IPC1-7):03K17/22 主分类号 H03K17/22
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