| 摘要 |
PURPOSE: To utilize a parts relatively low speed and low cost, e.g. CMOS by controlling the phase of a 2nd clock signal so as to correspond to one selected phase of plural delay clock signals. CONSTITUTION: A decoder receives a receiving data signal RD from a line 40, a carrier sensing signal CRC of a line 42, and a locally generating 10MHz clock signal of a line 44. The 10MHz clock input line 44 is connected to an with-tap delay line unit 52 capable of setting delay up to the maximum 100ns via a line 50. The output of the delay line unit 52 to an output line 54 is a PLL clock signal. The phase of the PLL clock signal is adjusted in from 0 deg. up to 360 deg. corresponding to a delay of from 0 ns up to 100 ns by selecting an appropriate tap in the delay line unit 52. |
