| 摘要 |
PURPOSE:To execute (2 X n)-bit operation between a memory and a register in one cycle by providing the arithmetic circuit with an arithmetic logic operation unit, a register, a multiplexer, and a latch and selecting the input of the arithmetic logic operation unit. CONSTITUTION:The arithmetic circuit is provided with a multiplexer 5 for selecting either one of data outputted from the 1st and 2nd memories 1, 2 and the data of the register 9 storing the arithmetic result of the arithmetic logic operation unit(ALU) 8, the data of the 2nd memory 2 and the data of the multiplexer 5 are respectively applied to the 1st ( 2 X n) input of the ALU 8, the upper or lower n bits of the 2nd (2 X n) input and the lower or upper n bits of the 2nd (2 X n) input at the same timing to execute (2 X n)-bit operation. Consequently, the operation of (2 X n) bits can be executed by one cycle. |
