| 摘要 |
<p>PURPOSE:To obtain an output equal to a conventional circuit from one memory and to save the scale of its control circuit by dividing an address of a counter into high-order and low-order and replacing them alternately at a period of NXN. CONSTITUTION:The complementary replacement of high-order and low-order bits in selectors 31, 32 is controlled by an address switching signal and a signal inverting the switching signal at an inverter 33. Levels '0', '1' of an address switching signal are selected at a period of 64 (8X8), and the address comprising of address high-order and low-order selected by the selectors 31, 32 is fed to a memory 13. The memory 13 outputs a data of the arrangement as shown in figure depending on the given address. Thus, a memory and its address control circuit to transpose a matrix data are constituted with a simple circuit and the save of the circuit scale is attained.</p> |
