| 摘要 |
A local bit clock having the frequency of the signal to be received is generated at the receiving end by means of a clock generator (TG) and a counter (Z). A phase evaluation logic (PAL) evaluates the time position of the leading edge of a received pulse in comparison with a predetermined time position of the effective pulse edge of the local bit clock. In the synchronous case, the effective pulse edge is located at the center of the received pulse (center-of-bit sampling). Because of nonideal line properties, the duration of the received pulses may differ from the desired value. To be able to distinguish a momentary edge drift of a received pulse (pulse too short or too long) from an actual phase shift, the time positions of the leading and trailing edges of each pulse are determined. If a pulse is too short or too long but symmetrical with respect to the predetermined time position of the effective pulse edge of the local bit clock, this indicates a momentary edge drift, so that no phase correction is necessary.
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