发明名称 SENSE AMPLIFIER CIRCUIT FOR SEMICONDUCTOR MEMORY
摘要 PURPOSE:To decrease the propagation delay time of a sense amplifier circuit almost without increasing energy consumption by operating a second serial circuit only for a fixed period including a time point, when an input signal to a sense amplifier is switched, after an address input signal is changed. CONSTITUTION:A serial circuit composed of pMOS Q6 and Q2a and nMOS Q4a and Q7 is parallelly connected to a serial circuit composed of a pMOS Q2 and an nMOS Q4 for load drive. When any one of address input signals A1, A2,..., An is changed, the change is detected and a pulse generating circuit 3 generates a one-shot pulse with certain fixed pulse width. This pulse becomes a control signal CS to control the Q6 and Q7 after passing through a delay circuit 4, and the Q6 and Q7 are conducted only during a certain fixed period. Thus, since the effective gate size of the load driving transistor is enlarged when the Q6 and Q7 are conducted, the propagation delay time of the sense amplifier circuit can be shortened.
申请公布号 JPH03142788(A) 申请公布日期 1991.06.18
申请号 JP19890280240 申请日期 1989.10.27
申请人 NEC CORP 发明人 TSUTSUI HIROAKI
分类号 G11C7/06;G11C11/41;G11C11/419 主分类号 G11C7/06
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