发明名称 SIGNAL PROCESSOR
摘要 <p>PURPOSE: To improve throughput by transferring data between a data recording mechanism and an arithmetic logic mechanism (ALU) and a cumulative multiplication mechanism (MACU) by placing data inside a register film and accessing the data by the expected reception of the data. CONSTITUTION: A register file 9 functioning as a general purpose buffer for an operand or a pool is provided and the simultaneous operations of the ALU 10 and the MACU 11 are made possible. Then, all operand transfer is performed from separated data storage mechanisms 6 and 7 through two separated buses to the register file 9 or from the file 9 to the storage mechanisms 6 and 7. The ALU 10 and the MACU 11 are provided with equal access rights at all times for all the data inside the file 9 and the file 9 also functions as a buffer for the result of a previous A'LU 10. The ALU 10 performs an arithmetic operation for the result for each operation and output from the MACU 11 is obtained for each operation of the ALU 10 when it is required. Thus, the throughput of this signal processor is improved.</p>
申请公布号 JPH03138759(A) 申请公布日期 1991.06.13
申请号 JP19900248983 申请日期 1990.09.20
申请人 INTERNATL BUSINESS MACH CORP <IBM> 发明人 GAADONAA DARANII JIYOONZU JIYUNIA
分类号 H03H17/02;G06F7/57;G06F9/38;G06F15/78;G06F17/10;G06F17/14 主分类号 H03H17/02
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