| 摘要 |
An analog-digital converter arrangement comprising i sigma-delta modulators (M0,...M5) which are activated by an analog input signal (E) and which output digital output signals (A) at a particular sampling rate, with i amplifiers (A1,...A5) which in each case precede the sigma-delta modulators, with i first sampling rate reducing devices (R0,...R5) which in each case follow the sigma-delta modulators, with i attenuating sections (D1,...D3) which in each case follow the sampling rate reducing devices and the attenuation factors of which are in each case equal to the inverse value of the gain factor occurring in the input circuit of the corresponding sigma-delta modulator, with a priority logic (PL) which, after evaluation of the signals of the sampling rate reducing devices, switches one of the signals through to the output, and with a second sampling rate reducing device (RA) which follows the priority logic.
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