| 摘要 |
A semiconductor memory device comprises a p--type semiconductor substrate (1), thin p+-type regions (15, 80) formed thereon, n+-type regions (6, 7) surrounded with the p+-type regions (15, 80), a first gate electrode (2) formed on a charge storage region in the n+-type region (6), and a second gate electrode (3) formed on the p+-type region (80) and serving as a word line. The p+-type regions (15, 80) prevent passage of electrons out of electron-hole pairs induced by alpha rays so as to prevent occurrence of soft errors. Advantageously, the thin p+ layer used to control threshold voltage for a transfer gate of the device is extended and also used for prevention of such soft errors, thus providing reduced bulk for the device. In order to reduce bulk further, the n+-type regions (6, 7) are also reduced in thickness. Films 16 and 17 are added to prevent an increase in diffusion resistance of the regions (6, 7) and the interconnection resistance of the second gate electrode (3). An oxide film (16) is formed on the side wall of the second gate electrode (3), a titanium silicide film (17) is formed on the n+-type regions (6, 7) and a titanium silicide film (18) is formed on the second gate electrode (3) in a self-aligning manner. A bit line is formed on the semiconductor region and connected thereto. An interlayer insulation film is optionally formed between the bit line and the refractory metal silicide film placed on the semiconductor n+-type region. The interlayer insulation film preferably comprises a silicon oxide film or a phosphorous oxide film. Finally, a protective film is optionally formed on the bit line. The protective film is preferably made of a material having a low dielectric constant.
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