发明名称 METHOD AND CIRCUIT FOR PROCESSING PULSE UNDER PILE-UP STATUS
摘要 PURPOSE: To process a preceding pulse and a succeeding pile-up pulse accurately by measuring the starting points of sampling and the pile-up pulse in relation with one frequency and its sub-frequency. CONSTITUTION: When the starting pulse that is generated at the time of the generation of a processing pulse 320, a first pulse train with a first pulse repetition frequency are generated 338, and a second pulse train with a second pulse repetition frequency 352 of the sub-frequency are generated from the train. Then, the starting points of a sampling 48 at the frequency 352 and a pile-up pulse 154 are measured 350 and 384 by measuring the state of the first and second pulse trains when the start pulse and the pile-up pulse are generated. Each pulse preceding the pile-up pulse is corrected by adding a residual tail sample by a signal processing circuit based on these, and each pile-up pulse is corrected by the subtraction of the tail sample due to the addition of the preceding pulse, thus performing pulse processing in pile-up condition.
申请公布号 JPH03135785(A) 申请公布日期 1991.06.10
申请号 JP19900251652 申请日期 1990.09.19
申请人 SIEMENS AG 发明人 ROJIYAA II AASENOO
分类号 G01J1/44;G01T1/164;G01T1/17 主分类号 G01J1/44
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